We gave a presentation at IEEE CoolChips 28 to clarify the positioning of the Agile-Chip Platform.
Venue：
TAKEDA Hall, The Univarsity of Tokyo, Japan
Overview：
The Agile-Chip Platform has been said to offer significantly lower development costs and shorter development times compared to conventional ASICs, but with disadvantages in performance and power consumption.
In this study, it was shown that Agile-2L, which utilizes a two-layer structure, can approach ASIC-level performance and power efficiency while significantly outperforming FPGAs. Even with the currently feasible single-layer structure, the Agile-Chip demonstrates slightly better performance and power consumption than FPGAs; however, due to its limited gate count, its applications are constrained to educational purposes.
The fact that these conclusions are based on quantitative evaluation makes this an important milestone for the project.
Responsibility: Amano
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