At the VDEC Refresh Seminar, we conducted an experiment to build simple digital circuits on a gate array using Minimal Fab.
Venue ：
Takeda Building, Asano Campus, the University of Tokyo
Overview：
At the VDEC Refresh Seminar, we conducted a hands-on exercise to build simple digital circuits using the gate array of the Agile-Chip Platform. The gate array section is designed using an automated design flow, enabling data exchange with the on-chip RISC-V processor. This was the first time that Minimal Fab was actually used for lithography. Six participants exposed their original circuits using Minimal Fab. Only the dry etching process was carried out later in a cleanroom.
Sumi, Shimamoto, Amano Responsibility: Amano
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